LFX Mentorship
Accelerating RISC-V vector instructions by using a bionic network design
RISC-V1 Program Years
Accelerating RISC-V vector instructions by using a bionic network design
Open Source
About the Organization
Software acceleration utilizing specifically designed hardware components is a widely used technique for speeding up different kinds of kernels found in the targeted applications. An example of such kernels in High-Performance Computing (HPC) are algorithms involving the computation of sparse data structures. Sparse applications are difficult to accelerate due to their memory-bound nature, which means that the data is not accessed contiguously in memory. That implies many scatter and gather accesses to the comparatively slow memory. Consequently, dedicated hardware components capable of accelerating the scatter/gather instructions, are a key to improve the performance of sparse applications. The goal of this project is to achieve an FPGA-based acceleration of the vrgather RISC-V vector instruction (RISC-V ISA vector extension v1.0) using a bitonic network. The bitonic network is originally a sorting network that implements the merge-sort algorithm (add reference here). A number of inputs of the network can end up in any output after traversing it. When this concept is applied to a Vector Register File, the bitonic network can be used not only to sort a set of vector elements, but also to move data internally from one register to any other register. The scope of this project is limited to the execution and acceleration of the gather vector instruction, in which the variability of the vector length needs to be considered.
Primary Technologies & Languages
rtl (system verilog, verilog or vhdl)rtl simulationcomputer architecturegit notionstclfpga design flowxilinx tools (vivado, vitis)risc-vfpga
Technical Topics & Focus Areas
rtl (system verilog, verilog or vhdl)rtl simulationcomputer architecturegit notionstclfpga design flowxilinx tools (vivado, vitis)risc-vfpga
Participation Years
Completed Projects Distribution
Annual Completed Projects History
Accelerating RISC-V vector instructions by using a bionic network designHover over bars to view completed counts
4
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1
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2022
Projects1
Years Active1
Stackrtl (system verilog, verilog or vhdl)
TierTier 1
Past Projects
Showing 1 of 1 projects. Click any project card for scope, mentors, and proposal studio.
Accelerating RISC-V vector instructions by using a bionic network design Mentorship Project
IntermediateSoftware acceleration utilizing specifically designed hardware components is a widely used technique for speeding up different kinds of kernels found in the targeted applications. An example of such kernels in High-Performance Computing (HPC) are algorithms involving the computation of sparse data structures. Sparse applications are difficult to accelerate due to their memory-bound nature, which means that the data is not accessed contiguously in memory. That implies many scatter and gather accesses to the comparatively slow memory. Consequently, dedicated hardware components capable of accelerating the scatter/gather instructions, are a key to improve the performance of sparse applications. The goal of this project is to achieve an FPGA-based acceleration of the vrgather RISC-V vector instruction (RISC-V ISA vector extension v1.0) using a bitonic network. The bitonic network is originally a sorting network that implements the merge-sort algorithm (add reference here). A number of inputs of the network can end up in any output after traversing it. When this concept is applied to a Vector Register File, the bitonic network can be used not only to sort a set of vector elements, but also to move data internally from one register to any other register. The scope of this project is limited to the execution and acceleration of the gather vector instruction, in which the variability of the vector length needs to be considered.