LFX Project

The RISC-V Mentorship Program enables one or more 12-week internship-style projects per session, funded by RISC-V, to match mentors/project leaders together with mentees/interns . Mentees are guided through a series of milestones by one or more project mentors, with whom the mentees meet on a weekly basis. Convolution is the core operation of deep learning models and computer vision applications. MLIR supports various convolution operations. Our project is to vectorize them for the RISC-V backend. There are several methods to implement convolution vectorization, such as optimizing nested loops, implementing vectorization algorithm, converting to GEMM, etc. This project needs to choose a vectorization method and implement a conversion pass for the convolution operations. As for the vector semantic support, MLIR has the “Vector” dialect for the general vector abstraction, and it also allows the backend-specific vector dialect, such as the “x86vector” dialect, “arm_neon” dialect, and “arm_neon” dialect. Like these dialects, the project also needs to propose an “RVV” dialect and work with existing dialects and tools. Deliverables: - An MLIR “RVV” Dialect. (Operations in the dialect can support the convolution vectorization) - A conversion pass to vectorize convolution operations in “Linalg” dialect with “RVV” dialect enabled. - A conversion pass to lower the operations in “RVV” dialect to “LLVM IR” dialect. - Unit tests for “RVV” dialect and conversion passes.

The RISC-V Mentorship Program enables one or more 12-week internship-style projects per session, funded by RISC-V, to match mentors/project leaders together with mentees/interns . Mentees are guided through a series of milestones by one or more project mentors, with whom the mentees meet on a weekly basis. Spidermonkey is the JavaScript Engine inside Firefox. It has JIT compilers for generating native binary codes on the fly. This project aims to porting Spidermonkey to RV64GC platform. Basic knowledge of compilers and language virtual machines are needed. Deliverables: - Cross-compile Spidermonkey to RV64GC Linux (Fedora) platform. - Patches that let Spidermonkey running on RV64GC Linux under interpreter mode. - Porting the baseline compilers so that Spidermonkey can enable at least one JIT compiler on RV64GC platform - Submit all patches to upstream for code review (merging into upstream is encouraged but not required) Acceptance criteria: - Pass the regression tests in the Spidermonkey. - Get performance data by running SunSpider, Octane and Kraken benchmarks on the RISC-V machine (RV64GC) or software simulator (QEMU).

The RISC-V Mentorship Program enables one or more 12-week internship-style projects per session, funded by RISC-V, to match mentors/project leaders together with mentees/interns. Mentees are guided through a series of milestones by one or more project mentors, with whom the mentees meet on a weekly basis. With this mentorship, the mentee will be performing formal verification of the SweRV-EL2 core (https://github.com/chipsalliance/Cores-SweRV-EL2) using riscv-formal (https://github.com/SymbioticEDA/riscv-formal). RISC-V formal has been applied for formal verification of picorv32 and Vexriscv cores that implement the RV32IMC Instruction set. Since the SweRV EL2 implements RV32IMC, it would be a good idea to formally verify it using RISC-V Formal. This would enable rapid adoption of the SweRV-EL2 core. Deliverables for this project include an open-source formal testbench for the SweRV-EL2 core that verifies the core correctly implements the RV32IMC instruction set. Additional formal checks can also be added.

The RISC-V Mentorship Program enables one or more 12-week internship-style projects per session, funded by RISC-V, to match mentors/project leaders together with mentees/interns . Mentees are guided through a series of milestones by one or more project mentors, with whom the mentees meet on a weekly basis. This program pairs one mentee with an experienced mentor to deliver a V8 JavaScript engine port for a 32-bit RISC-V core. The V8 JavaScript engine for RISCV64G has been upstreamed to Chromium recently. As a basic component for the Chromium web browser and node.js, it would enlarge RISCV’s application scenario. Although RV32G V8 port would be quite similar to RV64G V8 port , it is still in the TODO list. Porting and enable the RV32G on V8 will bring the embedded RISCV software ecosystem more applications, make RISC-V embed processors more competitive. Deliverables (bullet list of components and the changes expected): - Turbofan backend implementation - Embedded simulator implementation - Corresponding unit tests implementation - Regression tests pass Acceptance criteria (bullet list with measurable results defined): - RV32G cross-compiled and simulator build on both debug and release configuration should be passed - A helloworld demo should run successfully on both the embedded simulator and a real or emulated hardware (i.e. a real board or QEMU emulation). - 97% of the regression test should pass