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<p>Libraries for <a href="https://github.com/apple/swift-log" target="_blank">Logging</a> and <a href="https://github.com/apple/swift-metrics" target="_blank">Metrics</a>, embraced by the Serverside Swift Work Group, have enabled many Swift projects to simplify their code bases by removing their own implementations. However, there’s currently no official story for distributed tracing.</p> <p>This project aims to kick off the work on a distributed tracing infrastructure for the Swift ecosystem by creating a context propagation library with integration points for Swift NIO, AsyncHTTPClient, Swift gRPC, URLSession, and more.</p>

Utilizing cloud FPGAs prove to be very expensive and minor coding bugs could consume precious compute cycles and incur hefty bills. This proves using FPGAs on AWS F1, virtually ineffective for students, enthusiasts and early researchers. Additionally, 1st CLaaS, already has a streaming interface in place, not all hardware accelerators would require continuous streaming of data. The addition of support for Memory Mapped Interfaces like AXI4, AXI4 Lite, Wishbone and custom interfaces similar to RoCC, Core-V eXtension interface etc., would enable a wider ecosystem of hardware accelerators to support 1st CLaaS integration without any RTL Level modifications. Besides these, supporting 1st CLaaS on Local FPGAs/Remote FPGAs contrary to AWS F1 would prove useful to enthusiasts, researchers, professors and students having FPGA on-premise or remotely accessible. 1st CLaaS for PYNQ leverages the PYNQ (Python Productivity for Zynq) Framework, which consists of a Jupyter Server running in a Linux Operating system on the ARM Processor in the Zynq SoC. Addressing the current limitations of 1st CLaaS, the proposed framework that not only brings 1st CLaaS to PYNQ FPGAs, but also vendor agnostically automates TL-Verilog/Verilog/SystemVerilog based Hardware accelerator design from RTL to bitstream and deployment eliminating the need to interact with a wide range of vendor specific tools. The framework would provide a complete FPGA based hardware design flow within the browser/terminal right from designing in makerchip-app and IP-Block design-Bitstream generation to deployment on FPGA in a single command.

<p>The project aims at dealing with the conversion of <strong>CiceroMark to DOCX (OOXML) and vice versa</strong>. In the first portion, we are gonna improve the add-in by improving the existing features and addition of new features which generally includes the ergo expressions and inline blocks of a template. Apart from these, there will be testing of data to ensure that the correct data is entered into the variable fields to avoid any inconsistency. The second portion involves the conversion of the <strong>OOXML to CiceroMark</strong>. In this, improvements will be made to the OOXML transformer present <a href="https://github.com/accordproject/markdown-transform/tree/algoo-ooxml" target="_blank">here</a>. The current transformer works only for very basic OOXML. We need to extend the functionalities of the transformer to support more ciceromark and commonmark classes like lists, optional, inline, ergo formula blocks. In this way, we will ensure more flexibility and portability with the round trip transformation of the smart clause templates.</p>

Swift's concurrency runtime has no mechanism to enumerate live Tasks and TaskGroups. When a program using async/await stalls, existing tools such as thread backtraces, Instruments, LLDB are silent about the suspended tasks that are the likely cause. Instruments records task lifetimes after completion; there is no API, debugger command, or crash report field that answers "what tasks exist right now and what are they waiting on?" This project implements a global registry of live AsyncTask and TaskGroup instances inside the Swift Concurrency runtime. The core challenge is doing this without introducing unacceptable synchronisation overhead on every task creation and destruction, a hot path in any concurrent Swift program. I will implement and benchmark at minimum two candidate data structures: a sharded-mutex intrusive list (using PrivateStorage, which is opaque externally and safe to extend without breaking ABI) and a lock-free Treiber stack alternative. Deliverables: A working registry implementation with hooks in swift_task_create_commonImpl and AsyncTask::~AsyncTask() A design document comparing candidate data structures with measured overhead against the existing TaskGroups.swift and AsyncTree.swift benchmark suite Signal-safe crash backtrace integration listing live tasks on crash LLDB Python macros for interactive task inspection.

This project extends the Accord Project Template Playground by implementing an end-to-end, sandboxed logic execution pipeline to solve its inability to test interactive smart contract behaviors natively. By utilizing a secure Web Worker architecture, the platform will safely evaluate user-authored TypeScript logic and validate all states and requests against strict Concerto models directly in the browser. The core deliverables include an integrated Monaco-powered logic editor, an interactive contract runner UI for initialization and request handling, dynamic execution results visualization, and comprehensive multi-state contract templates. Together, these features transform the platform from a static authoring tool into a complete, interactive development workspace for smart legal contracts.

<p><a href="https://www.librecores.org/" target="_blank">LibreCores.org</a> lists free and open source "IP Cores" on the website for the community to view and use. Currently the website extracts the project readme and license and renders them on the project page, along with links to the project homepage and git repository.</p> <p>A user browsing for cores on LibreCores will be interested to know the quality of the project’s code so as to determine how useful the project will be to them. A part of such information can be inferred from the project's source code repository and activity in issue trackers. Also, these metrics may be put to use in search ranking in the future.</p> <p>In this project I worked on collecting and visualizing metrics about project quality of projects listed on LibreCores.org. These metrics include the frequency of code commits, activity in issue trackers, code quality, presence of documentation in code and contributors to the project.</p>

<p>This proposal aims to bring scripting support to SwiftPM. The goal for GSoC is some kind of proof-of-concept and is expected to be the foundation of a full implementation of this feature. The outcome is expected to be a prototype of the new <code>swift-script</code> tool, which has a limited set of basic operations implemented like <code>run</code> and <code>reset</code>. There will also be a new flag for Swift Driver which enables a shortcut to the feature through <code>swift</code> command.</p>

Accord Project Playground: Empowering Developers Through Interactive Learning Problem: The Accord Project offers powerful functionalities for smart legal contracts, but grasping these concepts can be challenging for developers with varying backgrounds. Existing documentation and resources may not provide an engaging and interactive learning experience. Solution: Proposing and developing a user-friendly Accord Project Playground. This web-based platform will provide an interactive environment for developers to experiment with Accord Project features through: Modern UI/UX Design: An intuitive and visually appealing interface that aligns with the Accord Project's branding. Interactive Code Samples: Live code editing and preview capabilities to demonstrate functionalities in a hands-on manner. Integrated Learning Resources: Comprehensive documentation, tutorials, and search functionality for efficient learning. Sample Management: Functionality to save and export user-created Accord Project code (specific format to be determined). Integration of Live Chat-Bot. Open-Source Principles: Adherence to open-source best practices for transparency, collaboration, and maintainability. Deliverables: * A fully functional Accord Project Playground website with interactive learning features. * Comprehensive documentation for the playground itself, including installation, setup, and usage guides. * A well-structured codebase with clear version control and adherence to coding standards. * A thriving contributor's community with a contributor's guide outlining participation procedures. Impact: By creating this Accord Project Playground, I aim to: * Lower the barrier to entry for developers interested in Accord Project technology. * Foster a more engaged and active Accord Project developer community. * Enhance the overall accessibility and user experience of the Accord Project.

Large digital designs are prone to consume lots of power and thus, a tool for power analysis is needed. There are two types of power analyses: static, which is more of an estimation that ignores circuit operations, and dynamic, which simulates the circuit behavior in conjunction with switching power. These tools are Verilog gate level-simulations and SPICE simulations, respectively, but the former can be inaccurate while the latter is computationally demanding. IRSIM, a tool intermediate between these two simulation tools, simulates the circuit as a network of transistor capable of turning ON and OFF, serving as a tradeoff between speed and accuracy in dynamic power analysis. The goal of this project is to develop and enhance a command-line interface compatible with up-to-date transistor components in the IRSIM library to ensure the analysis accounts for various power domains.

<p>The goal of the project is to automate and augment the verification of the custom FPGA and the bitstream with Cocotb, an open-source framework for verifying VHDL/ Verilog RTL using python. At the end of the project, users will get to generate a bitstream file and also know whether it is correct or not automatically.</p>

<p>This project will focus on a current problem in the Hardware community: The speed of RTL Simulations. These types of simulations are a necessary step in any hardware design. It is intrinsically a hard problem, and even commercial simulators run slow compared to the real hardware, which can be several orders of magnitude faster. On the open-source side, Verilator is one of the most famous players and offers a competitive simulation speed time compared to the closed-source ones. We will base our work on this tool. This project will consider that modern processors rely on Network-On-Chip (NoC) to communicate several cores in the same chip. The idea would be to use this hardware partition into consideration and make a stand-alone simulation per core and communicate through OpenMPI. This could potentially enable the simulation of a 1000-core processor, something currently unmanageable.</p>

<p>With this proposal I hope to benefit the open-source hardware enthusiast community with work related to the incredible Parallela board used by thousands of students and hobbyists around the world. This project will focus on the integration of the RISC-V rocket core, inside the Zynq FPGA device of Parallela. The RISC-V rocket core is an implementation of the RISV-V ISA that has gotten a lot of attention and support due to being clean, modular and power efficient. This project will allow owners of Parallela boards to write and execute RISC-V programs with minimal effort from their side. The system will work out of the box with a prebuilt binary image ready to be placed in an SD card and users will be able to re-build it with minimal effort. Moreover, a tutorial document will be created to aid inexperienced users make the most of this work and allow them to modify it for their own needs and purposes with custom hardware and / or software code.</p>

Deploying AWS Lambda functions using AWS SAM (Serverless Application Model) requires manual creation of a deployment descriptor, posing challenges for Swift developers due to learning a new DSL and adopting new tools like SAM CLI and Docker. To simplify this process, the community proposed a Swift-based DSL and a Swift package plugin. However, these solutions rely heavily on accurately mimicking the evolving SAM AWS deployment descriptor. To address this, this project proposes to automatically generate the AWSLambdaDeploymentDescriptor library based on the SAM template definition. That generated code is used by the Swift-based DSL to create SAM YAML templates required to deploy Lambda functions and their dependencies to AWS.

<p>JuxtaPiton is an architecture being developed at Princeton’s Parallel Group for heterogeneous ISA research. For this project, I will replace the existing PICORV32 core with the open-source ao486 core to have x86 ISA support along with the OpenSPARC T1’s SPARC V9. This kind of a heterogeneous system enables reuse of a lot of legacy x86 code. We also try to interface the L1 cache level of ao486 with the L1.5 cache subsystem of OpenPiton. This allows us to harness Piton’s P-Mesh subsystem which maintains cache coherency across both the cores.</p>

<p>The WARP-V is an open-source and highly configurable, adaptable, and flexible Core generator. It supports various ISA like MIPS, Open-Source RISC-V, and can even be configured with custom ISA. It is designed using emerging “Transaction-Level” modeling that takes advantage of advanced digital design features, timing-abstract nature of language features provided by TL-Verilog. My Project Proposal to harness its advantages and develop support for the multicore NoC design creating a custom kernel interface and deploying it on the cloud via the already existing 1st CLaaS framework. This project will not only lead to a highly configurable many-core hardware accelerator but it will also serve to motivate the industry toward FPGA-accelerated web applications and FPGA-accelerated cloud computing and also to demonstrate the flexibility of TL-Verilog and WARP-V to motivate the industry toward better design methodology.</p>

<p>Black Parrot is a tiny, modular Linux capable open-source processor core that encourages external contributions and strives for infrastructure agnosticism. It has been previously taped out successfully on commercial nodes TSMC 40nm and GlobalFoundaries 12nm. Last year, Google released the Google-Skywater 130nm Open-Source PDK which opened new windows in the field of Semiconductor Design and Manufacturing. To be able to successfully get a reliable, tiny, and modular Linux-capable processor like Black Parrot onto Skywater, and have it working, would be a key milestone for the open-source technology node. The aim of this project is to get a single-core implementation of Black-Parrot tapeout-ready on the Google-Skywater 130nm node.</p>

circt-bmc can already prove when an assertion is falsifiable, but it does not yet produce the counterexample trace format hardware developers rely on for debugging. Today, users get a SAT/UNSAT result without a practical cycle-by-cycle waveform showing how the design reached failure. This project adds that missing debugging path. I will preserve meaningful signal identities before lowering, track the corresponding solver expressions across BMC timesteps, and evaluate those expressions against the first satisfying Z3 model. The implementation is intentionally staged: first a readable text counterexample for the failing prefix, then VCD waveform generation from the same trace data. The focus is the first-failure prefix (cycle 0 to the violating step), which delivers high user value with low integration risk and clean upstreamability. Deliverables: 1. Signal tracking and naming pipeline for user-relevant values (ports, externalized registers, selected internals where remapping is reliable). 2. A BMC trace runtime component that records per-step solver ASTs and supports model-driven trace emission. 3. Midterm milestone: first-failure text counterexample dump. 4. Final milestone: VCD waveform output for the same counterexample path, exposed through circt-bmc CLI flags. 5. Upstream-quality tests and documentation (IR-level + end-to-end regressions, including failing and no-violation cases).

The project aims to add an exporter plugin for PeakRDL that enables a high level visualization for control & status register (CSR) design using Makerchip’s IDE and the visual debug (VIZ) framework. Makerchip provides an IDE for TL-Verilog design and simulation, where special JavaScript code can be written (VIZ Model) alongside the design to add a higher level of signal visualization that helps in simulation debugging.

<p>This project aims to develop user interactivity on the website through a full-fledged notification system and a platform to record user feedback. The notification system will be used to notify users associated with events and by the community to convey information to their audience i.e. the users, and the user feedback system will be used to determine the project quality/popularity amongst the developers.</p>

<p>Analysis of the architectural performance of WARP-V using FireSim and RocketChip Chisel code. Adding WARP-V to RocketChip to utilize the capabilities of RocketChip in generating a whole SoC. Integrating WARP-V with RocketChip components: L1 Cache, TLB and Page table walker to make RocketChip, WARP-V version, able to run Linux. then running RocketChip, WARP-V version, on FireSim to analysis the performance of WARP-V.</p>

This project enhances the console output experience for the Swift Testing framework by designing and implementing a new, two-phase console reporter. This architecture provides both real-time feedback during test execution (the "Live Phase") and concludes with a comprehensive, structured report (the "Summary Phase"). The primary focus during this GSoC project was the implementation of the Summary Phase, which includes: - A rich Hierarchical Summary that visualizes the relationship between test suites and individual tests. - A dedicated Detailed Failure Report providing clear, actionable information for debugging. - Intelligent cross-platform support, with an ASCII fallback for terminals with limited Unicode compatibility. Architecturally, the reporter was refactored to consume a serialization-based event stream (ABI.EncodedEvent). This was a significant technical pivot that decouples the reporter from the test runner, preparing it for future integration into an out-of-process "harness". The final deliverable is a robust, experimental implementation available behind a feature flag, with a clear roadmap for completing the Live Phase post-GSoC.

Considering the performance, instead of reparsing the entire file every time, we could speed up the parsing procedure with the information provided by old AST, which is an ability provided by the old parser. In the old implementation, this feature was only applied to CodeBlockList and MemberDeclList. In the new implementation, It would be nice to apply node reusing to other syntax collections e.g. exprList, functionParameterList, etc. Also, It would be good to allow more fine-grained reusable nodes via expanding the definition of nodeAtCursorCanBeReused to allow reusing nodes such as FunctionDeclSyntax where only identifier is changed.

<p>I'm proposing the creation of a Math Library for BaseJump STL. Adding a set of routines that employ the CORDIC algorithm to implement directly and indirectly computable functions like logarithmic, exponential, sqrt, etc. An overall better parameterization of bit-widths in the existing and new modules, along with functions that directly compute on an array with computations based on a configurable pipeline structure. I also propose to add explicit parallelization inspired by SIMD architecture to the mathematical functions in which the number of independent parallel data elements and bit-length is added as a parameter.</p>