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I will be developing a native Swift Memcached client using SwiftNIO to address the need for an efficient and user-friendly caching solution in Swift based applications. The goal is to provide a high performance client that integrates seamlessly with existing Swift ecosystems, simplifying the process of sending commands and receiving responses from memcached servers. Our focus is on implementing the Memcached meta protocol, request encoding, response decoding, and request pipelining, while the non-goals is to cover every memcached feature or command. This project aims to benefit developers by offering an asynchronous-first Swift API for essential memcached operations, ultimately enhancing the caching capabilities of their applications.

The swift-java interoperability library provides the jextract-swift tool, which extracts Java sources that are used to call Swift code from Java. However, the tool uses the Foreign Function and Memory API (FFM), which requires JDK 22+, making it unavailable on platforms such as Android. The goal of this proposal is to extend the jextract-swift tool, such that it is able to generate Java sources using JNI instead of FFM and thereby allowing more platforms to utilize Swift/Java interoperability. The solution will modify the code generation to support multiple modes through a protocol. Thereby, allowing us to generate JNI Java wrappers that that utilize the JNI functionality already defined in the library. We will modify the current Arena implementations to support memory management for JNI as well, through calls to the Swift runtime. The library will also generate Swift thunks that implement the native methods defined in Java and handle JNI/Swift conversion and object initialization. The project will achieve feature parity with the current FFM mode and explore more complex language features, if time permits.

Deploying AWS Lambda functions using AWS SAM (Serverless Application Model) requires manual creation of a deployment descriptor, posing challenges for Swift developers due to learning a new DSL and adopting new tools like SAM CLI and Docker. To simplify this process, the community proposed a Swift-based DSL and a Swift package plugin. However, these solutions rely heavily on accurately mimicking the evolving SAM AWS deployment descriptor. To address this, this project proposes to automatically generate the AWSLambdaDeploymentDescriptor library based on the SAM template definition. That generated code is used by the Swift-based DSL to create SAM YAML templates required to deploy Lambda functions and their dependencies to AWS.

<p>Block-Based Circuit Design is a solution to counter the complexity of Circuit Design. We aim to develop and deploy a Block-Based TL-Verilog solution for developers and new entrants to the sphere. Powered by Blockly from Google, it will deliver a simple, concise, and intuitive gateway to Circuit Design.</p>

<p>This project is to add Microarchitectural enhancement of Ariane that is a popular open-source CPU core implementing the RISC-V ISA (instruction set architecture). Currently, the processor is single-issue, meaning that the processor can only issue one instruction per clock cycle. That is a huge performance bottleneck since most functional units in the processor will stay idle when it does not have any instructions to proceed. In this project, I will implement super-scalar issue logic which allows Ariane to issue two (or more) instructions in the same clock cycle so that the overall performance will be greatly improved.</p>

<p>QEMU is a free and open virtual machine software that can be useful for the OpenRISC community for testing and teaching software development on the platform.</p> <p>The idea is to provide full support of the OpenRISC platform with some software already (the Linux operating system) and other devices, all running efficiently on the host system.</p> <p>Alongside with the software, documentation should be provided, to guide the community and (especially) beginners on how to use the platform to development and testing.</p>

This project aims to enhance the OpenPiton+Ariane architecture to progress toward RISC-V RVA23 profile compliance. The primary focus will be implementing the Svnapot extension, which allows for Naturally Aligned Power-Of-Two regions in memory to improve TLB efficiency. I will modify the CVA6 Memory Management Unit (MMU), specifically the Page Table Walker (PTW) and Translation Lookaside Buffer (TLB), to support this extension. As stretch goals, I plan to implement additional supervisor extensions required for RVA23 compliance, such as Svpbmt (Page-Based Memory Types) and Svadu (Hardware Updating of A/D Bits). The project will include comprehensive testing and documentation, ensuring all implementations conform to RISC-V specifications while integrating seamlessly with the existing architecture.

This project extends the Accord Project Template Playground by implementing an end-to-end, sandboxed logic execution pipeline to solve its inability to test interactive smart contract behaviors natively. By utilizing a secure Web Worker architecture, the platform will safely evaluate user-authored TypeScript logic and validate all states and requests against strict Concerto models directly in the browser. The core deliverables include an integrated Monaco-powered logic editor, an interactive contract runner UI for initialization and request handling, dynamic execution results visualization, and comprehensive multi-state contract templates. Together, these features transform the platform from a static authoring tool into a complete, interactive development workspace for smart legal contracts.

Throughout this project, I hope to gain a firmer understanding of TCL scripting and the backend working of parameterized devices and hopefully make some new ones too these devices are used many times while using magic to makes our work easier. this project will help me in a deeper understanding of how each command in the command line works in magic and how we can make some changes in its scripts to make it to improve user inference. In terms of the project, the goal is to work in scripts to draw devices like LDNMOS, LDPMOS, bipolar transistors, photodiodes, Avalanche Diode, etc as well as fixing a few devices that are known to draw incorrectly for some parameter values.as far as working on this project is concerned as per my own rough timeline following is the methodology i would use while working on the project : The magic VLSI tool uses TCL scripts for the parameterized design layouts so we should start by going through some of the scripts to get a better understanding of what we are working with then we will be going through each of the mentioned devices and study its CMOS design and draw it on the magic tool using the magic command line TCL scripts, we will also be looking at the pre-existing devices to check if we were getting the required drawings of them or not if the drawings are not as required then we will be making changes to those scripts as well, in the meantime, we will be looking for improvements we could make on the user inference of magic tool too. to get a better understanding of how I would work on this project please go through the proposal I have attached below. thankyou soo much for your time, looking forward to working with you soon.

circt-bmc can already prove when an assertion is falsifiable, but it does not yet produce the counterexample trace format hardware developers rely on for debugging. Today, users get a SAT/UNSAT result without a practical cycle-by-cycle waveform showing how the design reached failure. This project adds that missing debugging path. I will preserve meaningful signal identities before lowering, track the corresponding solver expressions across BMC timesteps, and evaluate those expressions against the first satisfying Z3 model. The implementation is intentionally staged: first a readable text counterexample for the failing prefix, then VCD waveform generation from the same trace data. The focus is the first-failure prefix (cycle 0 to the violating step), which delivers high user value with low integration risk and clean upstreamability. Deliverables: 1. Signal tracking and naming pipeline for user-relevant values (ports, externalized registers, selected internals where remapping is reliable). 2. A BMC trace runtime component that records per-step solver ASTs and supports model-driven trace emission. 3. Midterm milestone: first-failure text counterexample dump. 4. Final milestone: VCD waveform output for the same counterexample path, exposed through circt-bmc CLI flags. 5. Upstream-quality tests and documentation (IR-level + end-to-end regressions, including failing and no-violation cases).

The project aims to add an exporter plugin for PeakRDL that enables a high level visualization for control & status register (CSR) design using Makerchip’s IDE and the visual debug (VIZ) framework. Makerchip provides an IDE for TL-Verilog design and simulation, where special JavaScript code can be written (VIZ Model) alongside the design to add a higher level of signal visualization that helps in simulation debugging.

The project aims to integrate RISC-V Cache Management Operation (CMO) extensions into the OpenPiton processor framework. This integration will improve cache coherency and management, resulting in enhanced performance and efficiency for systems built on the OpenPiton platform. The project will involve understanding the RISC-V CMO specifications, modifying the OpenPiton cache subsystem, and extensive testing to ensure compatibility and performance improvements.

The goal of this project is to enhance the usability of Decorator Command Set (DCS) data by developing a utility/method to convert verbose, complex JSON formats into a more human readable YAML representation and back again. Currently, it is highly verbose to read, write, and edit DCS JSON files. The plan is to implement a converter that turns DCS JSON objects into a simple YAML format and back again. The new YAML will be less verbose and more readable, helping people work with DCS better. By the end, a fully integrated converter will be delivered, complete with tests and proper documentation.

<p>The open-source RISC-V instruction set architecture is gaining interest throughout industry and academia. One advantage of RISC-V is the ability to add custom instruction extensions to the processor targeting specific applications. A joint project between Embecosm and Southampton university recently developed an open source ISA extension for the CV32E40P RISC-V core to accelerate neural network inference acceleration (<a href="https://github.com/AI-Vector-Accelerator" target="_blank">https://github.com/AI-Vector-Accelerator</a>). The verification of the AI vector extensions project currently exists only as a Verilator model, and speed ups are based on cycle counts, with no insight to any impact on clock speed in actual silicon. There is no pipeline and everything is single cycle because there are no timing constraints in Verilator. This project aims to take the existing work and bring it up on a Nexys A7 FPGA platform.</p>

<p>Inlay hints take advantage of Swift's powerful type inference by visualizing inferred types throughout a Swift program in the editor. This makes it easier to read and understand Swift code, all while letting the programmer write concise code, without having to spell out every type. To achieve this, a custom LSP request is introduced that fetches the inferred types of unannotated variable bindings from the language server which, in turn, queries <code>sourcekitd</code> for the required information. The request will be called by the editor, e.g. VSCode, which will subsequently present the corresponding text decorations.</p>

Developing a native Swift-etcd client aims to seamlessly integrate etcd, a distributed Swift key-value store into Swift applications. This project aims to enable developers to have efficient communication with etcd servers via gRPC API, by targeting authentication, key-value operations, watch operations, and lease management.

When you design a digital circuit, you want to make sure that all timings are correct, even post-layout. Therefore, the gate level netlist is annotated with delays extracted from the layout. The file format that contains these delay and timing information is called Standard Delay Format (SDF). Icarus Verilogs' SDF implementation has shortcomings in the following categories: 1. Wire / Interconnect delays 2. Conditional path delays 3. Timing checks Work needs to be done on these categories, all while supporting related bugs as we more completely test gate level simulations. With the work proposed here, I would like to improve Icarus' SDF support to simulate SDF back-annotated timing simulations for the open SKY130 PDK. The deliverables for this project are: 1. Implementing the SDF `INTERCONNECT` feature 2. Writing tests for the regression suite 3. Example of a SDF back-annotated timing simulation using the SKY130 PDK

<p>This project involves a heterogeneous-ISA system based on a BYOC (Bring Your Own Core) framework. This provides a cache coherent, manycore research framework meant to support a variety of ISAs. The ao486 core having a x86 ISA, provides support for legacy code and is one of the few open source CISC ISAs. The initial approach to integration involved connecting BYOC through the Avalon interface. In this project, work is done with the bare interface of ao486 to interface it with BYOC to maintain cache coherency across all cores.</p>

<p>WARP-V is an emerging open-source CPU core generator for RISC-V CPUs. It benefits from the flexibility of Transaction-Level Verilog (TL-Verilog) to support a wide range of implementations from simple CPUs for FPGAs through high-frequency ASIC implementations. The goal of the project is to formally verify the WARP-V core, making development easier for the strict requirements of the RISC-V specification and enabling the use of the WARP-V core in highly demanding and critical areas.</p>

<p>Schematics are a great way to understand electronic circuits, and specially when we are using high level descriptions, it becomes essential that we are able to portray what we have in mind. Automatic schematic generation will allow us to generate publication quality schematics directly from HDLs (verilog in this case).</p> <p>The objective is to take input a circuit desciption in json format (generated by yosys tools), and automagically create a schematic for it. The algorithm will run on the client side, so there will be no need to send data to server (thus no privacy concerns). Moreover interactivity with the generated circuit will allow it to be used as a great tool for learning circuits and HDL.</p> <p>I plan to implement the core algorithm as library which can be easily extended to work with a variety of cases like</p> <ul> <li>Combining it with simulators to perform interactive simulations</li> <li>Using it to create non-electronic schematics</li> </ul>

Concerto, the core modeling language of the ACCORD PROJECT, is critical for smart legal contracts and domain modeling. This project aims to migrate from the current testing framework mocha to vitest which will enhance the performance, execution time and debugging capabilities. This process can be automated by the combination of vitest-codemod, regex transformations, ai assistance and some manual scripts required for handling complex test cases which cannot be automated. Here are the deliverables: 1. Migration from Mocha, Chai, Sinon to Vitest for all Concerto implementation. 2. A new Concerto conformance package which will be a standalone validation test package for all Concerto implementations.

<p>Field-Programmable Gate Array(FPGA) is a hardware circuit that a user can program to carry out logical operations. FPGAs are beneficial for prototyping application-specific integrated circuits (ASICs) or processors.</p> <p>The advantage of FPGA being energy-efficient, flexible to reprogram, support parallelism, decreased latency made them widely used in many applications. But the flexibility of FPGAs comes at the price of the difficulty of reprogramming the circuit. FPGA’s are a bit costly and difficult to learn for beginners. Also, students don’t have access to physical FPGA Lab classes in their curriculum amidst this pandemic situation. So there is a massive demand in having an alternative option of having an online simulator for FPGA curriculum development.</p> <p>This project aims to solve the problem by taking advantage of the VIZ Visualization feature in the Makerchip platform and provide visualizations of basic peripherals of an FPGA, thereby mimicking the physical lab experience.</p>

My proposal aims to make Sootty, a CLI waveform viewer, a more utilitarian and intuitive tool to use, by adding features that I believe it would benefit from. I propose to implement new features like flags for saving previously used queries and multiple trigger expressions to help make the tool more user friendly.