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This project is a practical application under the umbrella of the MLGO framework. While the previous work focuses on inlining and eviction policy of regAlloc, the project will explore a new application of MLGO on the priority policy of regAlloc, which could be a potential alternative to the manual-maintained heuristic.

<p>With a surge of machine learning, especially the neural network model which needs to compute a huge amount of gradients, more and more languages' users begin to call for the ability to do high-performance and convenient <em>automatic differentiation</em> (hereafter AD) on functions, whereupon many AD tools are developed, among which is Enzyme. Enzyme is made as a plugin of LLVM and synthesizes differentiated functions directly on optimized LLVM IR code, which provides it with advantages in efficiency and universality. From another aspect, Rust is an emerging high-performance and safe language. Many of its users are trying to bring machine learning to it, thus an high-performance and user-friendly AD tool needed. Enzyme is a good option for this demand. However, without a deep integration into Rust, Enzyme's user experience with Rust is not so good, and more importantly, it may suffer from performance reduction due to wasted Rust meta-information. These problems hamper Enzyme from being widely used in Rust. This project will tackle the aforementioned problems through integrating Enzyme into Rust and then provide high-performance differentiation in Rust.</p>

<p>The aim of this project is to complete all remaining typescript and webpack tasks in order to ensure a smooth development workflow. In particular:</p> <ul> <li>Remove all custom typings for typescript</li> <li>Remove "any" types for third-party libraries</li> <li>Remove all "any" types from the codebase</li> <li>Replace third_party and remaining imports with webpack</li> <li>Reduce the overall time for webpack compilation.</li> <li>Add documentation on all typescript and webpack errors and solutions on how to fix them.</li> </ul>

<p>Oppia uses Angular as the frontend framework with typescript as the primary language, hence this codebase is fully typed which implies that variable assignment, procedure arguments and function return values will all be associated explicitly with a type. <code>strict</code> is a typescript compiler option which turns on a set of stricter type rules which, when enabled, helps reduce the chances of getting unpredictable results and makes the code more robust but currently, Oppia’s code base does not pass these strict rules. This makes the code prone to unexpected actions and errors.</p> <p>To avoid this, the following actions need to be taken:</p> <ul> <li>All the new files to be added should have typescript strict mode enabled</li> <li>Strict typing should be introduced to the files already present in the code base</li> </ul> <p>This project aims to change the config files to ensure that any new file added to the Oppia’s code base will, by default, have typescript <strong>strict mode</strong> enabled. Also, strict typing will be introduced to 240 files (120 files and their test file) already present in the code base and listed down in <code>UpgradedServices.ts</code>.</p>

In order to streamline releases, we are planning to ensure that all critical user journeys (CUJs) on the Oppia web application are covered by acceptance tests. This is important because it will provide assurance that, on the merge of every PR, these critical user journeys still function correctly, which means that no major breakages will result if the develop branch gets deployed to production. Additionally, having a complete set of acceptance tests that are organized by CUJ makes it easier to audit whether or not a particular CUJ has been included, and it also helps developers add tests for new CUJs while still keeping the tests well-organized. This project includes: Writing acceptance tests for the as-yet-uncovered CUJs in a way that keeps the tests organized and maintainable. This might also include small updates to the acceptance test framework, e.g. extracting utility functions to enable code reuse or providing relevant functionality for a group of tests. Tightening all page utility functions to have pre/post checks (in the form of "wait" statements) and proper error messaging, so that it is easier to debug flakes. The pre-check wait ensures that the conditions are good for performing the action, and the post-check wait ensures that the action has fully completed. Deleting e2e tests whose functionality has been fully replaced by the acceptance tests.

<p>This project aims to introduce a system to introduce a suggestion-review system which would allow the community to contribute to the content on Oppia. It also aims to add a review system to allow easy management of the proposed suggestions and accept or reject them as appropriate. In order to maintain quality of reviews, we allow reviews from users who have made above a certain number of contributions in similar kind of suggestions. For each exploration the creator of the exploration can appoint some trusted reviewers who will be able to accept (merge) content related suggestions for that exploration. At a site-wide level, translation reviewers can be selected for each language and they can accept translations for that particular language.</p>

<p>As seen on Bazel’s <a href="https://github.com/bazelbuild/bazel/issues?utf8=%E2%9C%93&amp;q=is%3Aissue+is%3Aopen+NullPointerException+" target="_blank">Issue Page</a>, Bazel suffers from numerous <code>NullPointerException</code>( NPE ). These NPEs come out at runtime as <code>RuntimeException</code> causing a crash at runtime this leads to a large number of Issues being generated. This could be a result of not handling possible <code>null</code> values not being handled in many cases or outright poor design choices(as seen in many issues due to not handling <code>null</code> OR empty string as arguments while using certain flags).</p> <p><strong>Checker Framework's Nullness Checker</strong> runs as a compiler plug-in, and it issues a warning at every possible null pointer dereference. If it issues no warnings, the code is guaranteed not to throw a <code>NullPointerException</code> at run time.</p> <p>My project will ensure the significant reduction of these NullPointerException(s) before they happen (by checking them at compile time) rather than relying on users to report them and fixing them.</p>

This project aims to enhance the Checker Framework by introducing a Mutable Index Checker, which provides compile-time guarantees of index safety for dynamically sized data structures such as ArrayList, LinkedList, and Deque. Unlike the current Index Checker, which focuses on fixed-length structures like arrays and strings, this checker will track collection size changes across mutations, enabling flow-sensitive reasoning and validation of index accesses. The checker will support annotations like @IndexFor, @LengthOf, @SameLen, and custom subtyping rules to enforce both lower and upper bounds on index values. It will also provide support for aliasing-aware length consistency, post-mutation invalidation, and integration with purity annotations. Deliverables include: - A new pluggable type checker integrated into the Checker Framework. - Support for standard mutable collections with annotated APIs. - Type qualifiers and subtyping rules for index tracking. - Flow-sensitive analysis and invalidation logic on mutations. - Real-world examples, documentation, and a case study on annotating existing codebases. This tool will help developers prevent IndexOutOfBoundsException in mutable structures by enforcing correctness at compile-time—making Java applications safer and more robust.

Blendyn is one of MBdyn post-processing tools based on the Blender platform. It visualizes MBdyn output as a 3D system. However, the current Blendyn version is outdated since its last update is in 2017. In this project, we aim to flexible plotting engines and plotting features, and create a Live animation feature that visualizes MBdyn output in the real-time animation process. In addition to that, we also intend to make stress and strain visible for deformable objects.

<p>KIOSlaves are a powerful feature within the KIO framework, allowing KIO-aware applications such as Dolphin to interact with services out of the local filesystem over URLs such as fish:// and gdrive:/. However, KIO-unaware applications are unable to interact seamlessly with KIO Slaves. For example, editing a file in gdrive:/ in LibreOffice will not save changes to your Google Drive. One potential solution is to make use of FUSE, which is an interface provided by the Linux kernel, which allows userspace processes to provide a filesystem which can be mounted and accessed by regular applications. KIOFuse is a project by Fabian Vogt that allows the possibility to mount KIO filesystems in the local system; therefore exposing them to POSIX-compliant applications such as Firefox and LibreOffice. This project intends to polish KIOFuse such that it is ready to be a KDE project.</p>

circt-bmc can already prove when an assertion is falsifiable, but it does not yet produce the counterexample trace format hardware developers rely on for debugging. Today, users get a SAT/UNSAT result without a practical cycle-by-cycle waveform showing how the design reached failure. This project adds that missing debugging path. I will preserve meaningful signal identities before lowering, track the corresponding solver expressions across BMC timesteps, and evaluate those expressions against the first satisfying Z3 model. The implementation is intentionally staged: first a readable text counterexample for the failing prefix, then VCD waveform generation from the same trace data. The focus is the first-failure prefix (cycle 0 to the violating step), which delivers high user value with low integration risk and clean upstreamability. Deliverables: 1. Signal tracking and naming pipeline for user-relevant values (ports, externalized registers, selected internals where remapping is reliable). 2. A BMC trace runtime component that records per-step solver ASTs and supports model-driven trace emission. 3. Midterm milestone: first-failure text counterexample dump. 4. Final milestone: VCD waveform output for the same counterexample path, exposed through circt-bmc CLI flags. 5. Upstream-quality tests and documentation (IR-level + end-to-end regressions, including failing and no-violation cases).

<p>The open-source RISC-V instruction set architecture is gaining interest throughout industry and academia. One advantage of RISC-V is the ability to add custom instruction extensions to the processor targeting specific applications. A joint project between Embecosm and Southampton university recently developed an open source ISA extension for the CV32E40P RISC-V core to accelerate neural network inference acceleration (<a href="https://github.com/AI-Vector-Accelerator" target="_blank">https://github.com/AI-Vector-Accelerator</a>). The verification of the AI vector extensions project currently exists only as a Verilator model, and speed ups are based on cycle counts, with no insight to any impact on clock speed in actual silicon. There is no pipeline and everything is single cycle because there are no timing constraints in Verilator. This project aims to take the existing work and bring it up on a Nexys A7 FPGA platform.</p>

<p>I'm proposing the creation of a Math Library for BaseJump STL. Adding a set of routines that employ the CORDIC algorithm to implement directly and indirectly computable functions like logarithmic, exponential, sqrt, etc. An overall better parameterization of bit-widths in the existing and new modules, along with functions that directly compute on an array with computations based on a configurable pipeline structure. I also propose to add explicit parallelization inspired by SIMD architecture to the mathematical functions in which the number of independent parallel data elements and bit-length is added as a parameter.</p>

Throughout this project, I hope to gain a firmer understanding of TCL scripting and the backend working of parameterized devices and hopefully make some new ones too these devices are used many times while using magic to makes our work easier. this project will help me in a deeper understanding of how each command in the command line works in magic and how we can make some changes in its scripts to make it to improve user inference. In terms of the project, the goal is to work in scripts to draw devices like LDNMOS, LDPMOS, bipolar transistors, photodiodes, Avalanche Diode, etc as well as fixing a few devices that are known to draw incorrectly for some parameter values.as far as working on this project is concerned as per my own rough timeline following is the methodology i would use while working on the project : The magic VLSI tool uses TCL scripts for the parameterized design layouts so we should start by going through some of the scripts to get a better understanding of what we are working with then we will be going through each of the mentioned devices and study its CMOS design and draw it on the magic tool using the magic command line TCL scripts, we will also be looking at the pre-existing devices to check if we were getting the required drawings of them or not if the drawings are not as required then we will be making changes to those scripts as well, in the meantime, we will be looking for improvements we could make on the user inference of magic tool too. to get a better understanding of how I would work on this project please go through the proposal I have attached below. thankyou soo much for your time, looking forward to working with you soon.

This project aims to make contract execution easier by removing the need to write TypeScript logic for every template. Instead, it uses an LLM to understand the contract and execute it automatically. The system adds three modes—disabled, fallback, and force—so users can choose between normal typescript logic and LLM execution. It also includes proper validation and formatting to ensure correct outputs. The project will be tested on different real world templates and compared with existing logic to check accuracy and performance.

The project aims to integrate RISC-V Cache Management Operation (CMO) extensions into the OpenPiton processor framework. This integration will improve cache coherency and management, resulting in enhanced performance and efficiency for systems built on the OpenPiton platform. The project will involve understanding the RISC-V CMO specifications, modifying the OpenPiton cache subsystem, and extensive testing to ensure compatibility and performance improvements.

Apache Kafka is a distributed event streaming platform that is very widely used to process and store data. This project aims to create a Swift Package that enables Swift developers to send and receive data in the Kafka ecosystem while also taking advantage of the new Swift Concurrency features. At first, this shall be achieved by wrapping an existing C library called librdkafka.

<p>QEMU is a free and open virtual machine software that can be useful for the OpenRISC community for testing and teaching software development on the platform.</p> <p>The idea is to provide full support of the OpenRISC platform with some software already (the Linux operating system) and other devices, all running efficiently on the host system.</p> <p>Alongside with the software, documentation should be provided, to guide the community and (especially) beginners on how to use the platform to development and testing.</p>

<p>This proposal aims to bring scripting support to SwiftPM. The goal for GSoC is some kind of proof-of-concept and is expected to be the foundation of a full implementation of this feature. The outcome is expected to be a prototype of the new <code>swift-script</code> tool, which has a limited set of basic operations implemented like <code>run</code> and <code>reset</code>. There will also be a new flag for Swift Driver which enables a shortcut to the feature through <code>swift</code> command.</p>

Efabless, Google, and SkyWater Technologies, through the Open MPW and ChipIgnite programs, provide free ASIC fabrication. To help streamline the development flow. This project aims at the creation of the starting template for the development of the projects using the free online Makerchip IDE. The project template will include the visualization of the Caravel harness using the Makerchip’s visual debug feature which will make debugging user designs very easy as compared to the default waveform viewers. This project will also include the support for FPGA prototyping by using the Virtual FPGA labs which have been created using visual debug. The sample user project is used by the open-source designs for the MPW submissions so the proposed project will also involve build flow enhancements to the Caravel sample user project by adding support for TL-Verilog and the Makerchip.

<p>This project aims to develop user interactivity on the website through a full-fledged notification system and a platform to record user feedback. The notification system will be used to notify users associated with events and by the community to convey information to their audience i.e. the users, and the user feedback system will be used to determine the project quality/popularity amongst the developers.</p>

<p>Librecores provides a platform to share projects and ideas, in the area of free and open source digital hardware design. Librecores CI is an approach/service to provide continuous integration to hardware projects hosted on Librecores to improve user experience and reliability. This project aims to provide automation service for some hardware projects that have a constantly evolving code. Jenkins, the automation server will be used to achieve the goals of the project.</p>

Add a vectorization support to Arcilator. An efficient vectorization pass will make Arcilator faster, as hardware designs often contain highly repetitive structures that require the same computation on different data pieces. The proposed pass will implement most of the Superword Level parallelism features. This project starts by packing the seed operations and extending the pack sets as needed according to the cost function that calculates the benefit from packing and unpacking instructions.