LFX Mentorship
UETRV PicoCore
RISC-V1 Program Years
UETRV PicoCore
Open Source
About the Organization
"Overview: The UETRV PicoCore project aims to enhance the capabilities of the existing UETRV_Pcore RISC-V core, making it a versatile and feature-rich open-source microcontroller. The core is RV32IMA Linux-compatible and Privilege Architecture 1.10 compliant, and we envision integrating essential extensions such as bitmanip, floating point, debug, trace, and GPIO peripherals. This initiative aligns with the broader goal of providing a comprehensive RISC-V MCU solution that is accessible to the open-source community. Tasks: Bitmanip Extension Integration: The Bitmanip extension offers advanced bitwise manipulation instructions. The task involves integrating this extension into the existing UETRV_Pcore, optimizing its usage, and ensuring compatibility with existing codebases. Floating Point Extension Integration: Incorporating the Floating Point extension will enable hardware-accelerated floating-point computations. This task involves integrating the extension into the core, optimizing performance, and ensuring compliance with the RISC-V standard. Debug, Trace, and GPIO Peripherals: Enhancing the microcontroller's capabilities, this task involves integrating debug and trace functionalities for improved development and debugging. Additionally, GPIO peripherals will be integrated to facilitate easy interfacing with external devices.
Primary Technologies & Languages
risc-v architecturefpgaplatformioembedded systemsrisc-v
Technical Topics & Focus Areas
risc-v architecturefpgaplatformioembedded systemsrisc-v
Participation Years
Completed Projects Distribution
Annual Completed Projects History
UETRV PicoCoreHover over bars to view completed counts
4
3
2
1
0
2024
Projects1
Years Active1
Stackrisc-v architecture
TierTier 1
Past Projects
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An Extended RISC-V Microcontroller Core
Intermediate"Overview: The UETRV PicoCore project aims to enhance the capabilities of the existing UETRV_Pcore RISC-V core, making it a versatile and feature-rich open-source microcontroller. The core is RV32IMA Linux-compatible and Privilege Architecture 1.10 compliant, and we envision integrating essential extensions such as bitmanip, floating point, debug, trace, and GPIO peripherals. This initiative aligns with the broader goal of providing a comprehensive RISC-V MCU solution that is accessible to the open-source community. Tasks: Bitmanip Extension Integration: The Bitmanip extension offers advanced bitwise manipulation instructions. The task involves integrating this extension into the existing UETRV_Pcore, optimizing its usage, and ensuring compatibility with existing codebases. Floating Point Extension Integration: Incorporating the Floating Point extension will enable hardware-accelerated floating-point computations. This task involves integrating the extension into the core, optimizing performance, and ensuring compliance with the RISC-V standard. Debug, Trace, and GPIO Peripherals: Enhancing the microcontroller's capabilities, this task involves integrating debug and trace functionalities for improved development and debugging. Additionally, GPIO peripherals will be integrated to facilitate easy interfacing with external devices.