SymbiFlow

Mentors: Student: Arash Ahmadian

<p>Symbiflow has already produced a model of Xilinx's Artix7 in VTR, but it only limited to single chip description. The aim of this project is to instead investigate how to describe Artix7 at a higher level of abstraction, using VTR's architecture description language, so the chip definition can easily be changed to make conducting experiments with related architecture easier.</p>

Mentors: Student: Andrew Butt

<p>SymbiFlow does not currently support partial reconfiguration regions. Partial reconfiguration regions are crucial to ongoing FPGA research including reducing verilog to bitstream compilation times through separate compilation. Two major hurdles to the support of partial reconfiguration regions are SymbiFlow and VPR support for restricted placement/routing and the ability to generate and upload a partial bitstream. I will be taking on the first of these two hurdles.</p>

Mentors: Student: Shad Torrie

<p>The VTR (Verilog-to-routing) project provides an academic open-source CAD flow for FPGAs, combining tools for Synthesis and Logic Optimization (Yosys, ODIN, ABC), with tools for physical implementation (VPR). At the heart of this tool suite, is a set of scripts that manage the execution of coordinate of these tools. Currently, these scripts are written in a few different languages, but mostly in Perl. I am proposing converting the Verilog-to-routing test runner scripts from Perl to Python. While doing this I will make various optimizations and enhancements.</p>

Mentors: Student: Bingran Hu

<p>I will focus on the Vehicle-to-Routing (VTR) component of the SymbiFlow project. Specifically, I will work on improving the existing electronic design automation (EDA) tools that place and route various logic gates, flip-flops, look-up tables (LUT) and more complex logic blocks on the Field-programmable Gate Array (FPGA). Important evaluation factors are the speed of the optimization process and the quality of the final mapped design.</p> <p>Two major techniques that I will experiment with are:</p> <ol> <li>Providing a fast and decent preliminary placement solution that does not cluster remotely related logics.</li> <li>Allowing clusters to be taken apart and the primitives optimized during placement.</li> </ol>

Mentors: Student: Fahrican Koşar

<p>I propose replacing VPR’s XML reader for the architecture file with a schema-generated one. Furthermore, I propose replacing current rr_graph, top.net, route and place formats with more efficient binary formats. I’m planning to use FlatBuffers for top.net, route and place, and a custom, memory-mappable binary format for the rr_graph file.</p> <p>As an addition, I will investigate possibilities to generate the rr_graph in VPR from smaller pieces of information such as tilegrid.json and tileconn.json.</p>