LFX Mentorship Active 2026
RISC-V Vector Coprocessor for ECG Detection on UET-RVMCU
RISC-V1 Program Years
RISC-V Vector Coprocessor for ECG Detection on UET-RVMCU
Open Source
About the Organization
This project aims to develop and verify a custom RISC-V Vector (RVV) v1.0 compliant coprocessor to accelerate an Electrocardiogram (ECG) detection algorithm. Building on our previous work with a CGRA accelerator, this project addresses its key limitations by leveraging the standardized RISC-V Vector extension, which offers superior toolchain support and predictable data-level parallelism. The mentee will focus on two core pillars: 1. Verification and Integration of RVV Modules: Rigorously test and integrate pre-designed hardware modules to build a functional vector coprocessor. 2. Algorithm Development: Implement and optimize vectorized ECG signal processing kernels using RVV intrinsics.
Primary Technologies & Languages
system verilogriscv-isapipelininggit
Technical Topics & Focus Areas
system verilogriscv-isapipelininggit
Participation Years
Completed Projects Distribution
Annual Completed Projects History
RISC-V Vector Coprocessor for ECG Detection on UET-RVMCUHover over bars to view completed counts
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2026
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Past Projects
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RISC-V Vector Coprocessor for ECG Detection on UET-RVMCU Mentorship Project
IntermediateThis project aims to develop and verify a custom RISC-V Vector (RVV) v1.0 compliant coprocessor to accelerate an Electrocardiogram (ECG) detection algorithm. Building on our previous work with a CGRA accelerator, this project addresses its key limitations by leveraging the standardized RISC-V Vector extension, which offers superior toolchain support and predictable data-level parallelism. The mentee will focus on two core pillars: 1. Verification and Integration of RVV Modules: Rigorously test and integrate pre-designed hardware modules to build a functional vector coprocessor. 2. Algorithm Development: Implement and optimize vectorized ECG signal processing kernels using RVV intrinsics.