LFX Mentorship Active 2026
RISC-V Processor Certification
RISC-V1 Program Years
RISC-V Processor Certification
Open Source
About the Organization
The RISC-V Certification Steering Committee is developing certification tests to prove that RISC-V processors conform to the ratified specifications. The goal of this mentorship project is to run the tests on as many open-source RISC-V cores as possible, and improve the usability of the tests, debug any issues found in the tests, and report any real bugs that might be found in the cores. This work will involve: * Identifying multiple open-source cores to test * For each core: - Develop a Unified Database (UDB) file specifying the extensions and parameters supported by the core - Implement trick box macros to trigger interrupts, print characters to a console, and terminate a simulation in a core- specific manner - Create a linker script appropriate to the memory map of the core - Compile the tests with the core-specific trick box and linker scripts - Run the relevant tests on the core * Identify and fix any problems in the tests that make them hard to run on a core * Identify and fix any problems with the flow or documentation * Identify and report any bugs found in the cores The work will start with Phase 0 tests of the RVI20 profile with the RV{32/64}IMACDF extensions in machine mode. As time permits, it will continue to the Phase 1 MC100 microcontroller profile with machine mode, traps, Zicsr, and Zicntr, and then to the Phase 2 RVA23 application processor profile with all privilege modes, vector and hypervisor.
Primary Technologies & Languages
risc-v instruction setgcc toolchainsystemverilog simulationdebuggingself-motivated and able to learn new skills independentlyhave interests and skills related to both software and hardwareinterest in verification
Technical Topics & Focus Areas
risc-v instruction setgcc toolchainsystemverilog simulationdebuggingself-motivated and able to learn new skills independentlyhave interests and skills related to both software and hardwareinterest in verification
Participation Years
Completed Projects Distribution
Annual Completed Projects History
RISC-V Processor CertificationHover over bars to view completed counts
4
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1
0
2026
Projects1
Years Active1
Stackrisc-v instruction set
TierTier 1
Past Projects
Showing 1 of 1 projects. Click any project card for scope, mentors, and proposal studio.
RISC-V Processor Certification Mentorship Project
IntermediateThe RISC-V Certification Steering Committee is developing certification tests to prove that RISC-V processors conform to the ratified specifications. The goal of this mentorship project is to run the tests on as many open-source RISC-V cores as possible, and improve the usability of the tests, debug any issues found in the tests, and report any real bugs that might be found in the cores. This work will involve: * Identifying multiple open-source cores to test * For each core: - Develop a Unified Database (UDB) file specifying the extensions and parameters supported by the core - Implement trick box macros to trigger interrupts, print characters to a console, and terminate a simulation in a core- specific manner - Create a linker script appropriate to the memory map of the core - Compile the tests with the core-specific trick box and linker scripts - Run the relevant tests on the core * Identify and fix any problems in the tests that make them hard to run on a core * Identify and fix any problems with the flow or documentation * Identify and report any bugs found in the cores The work will start with Phase 0 tests of the RVI20 profile with the RV{32/64}IMACDF extensions in machine mode. As time permits, it will continue to the Phase 1 MC100 microcontroller profile with machine mode, traps, Zicsr, and Zicntr, and then to the Phase 2 RVA23 application processor profile with all privilege modes, vector and hypervisor.