LFX Mentorship
Performance Model of an Example RISC-V Out-of-Order Superscalar Processor for Community-wide Use
RISC-V1 Program Years
Performance Model of an Example RISC-V Out-of-Order Superscalar Processor for Community-wide Use
Open Source
About the Organization
RISC-V Performance Modeling SIG is driving the development of Performance Modeling and Simulation Tools for use across RISCV membership, to reduce duplication of effort and to foster collaboration. As such, we have developed a barebones performance model of an example RISCV superscalar processor using C++ based on Sparta simulation framework. We have also identified a clear set of features that need to be added to this model to make it more complete. In particular, we would like to add a branch predictor, register renaming and a memory subsystem hierarchy to the model. The identified set of features are listed here as issues in the repository: https://github.com/riscv-software-src/riscv-perf-model/issues We invite mentees who are passionate about computer architecture and performance modeling to join us in this effort. This is an excellent opportunity to develop a key piece of software that will have high visibility and utility across the entire RISCV community, both in industry and academia. This also presents an opportunity to work with veteran engineers from industry involved in this project.
Primary Technologies & Languages
computer architectureperformance modelingperformance analysiscollaborating with remote teamsc++
Technical Topics & Focus Areas
computer architectureperformance modelingperformance analysiscollaborating with remote teamsc++
Participation Years
Completed Projects Distribution
Annual Completed Projects History
Performance Model of an Example RISC-V Out-of-Order Superscalar Processor for Community-wide UseHover over bars to view completed counts
4
3
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1
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2023
Projects1
Years Active1
Stackcomputer architecture
TierTier 1
Past Projects
Showing 1 of 1 projects. Click any project card for scope, mentors, and proposal studio.
Performance Model of an Example RISC-V Out-of-Order Superscalar Processor for Community-wide Use Mentorship Project
IntermediateRISC-V Performance Modeling SIG is driving the development of Performance Modeling and Simulation Tools for use across RISCV membership, to reduce duplication of effort and to foster collaboration. As such, we have developed a barebones performance model of an example RISCV superscalar processor using C++ based on Sparta simulation framework. We have also identified a clear set of features that need to be added to this model to make it more complete. In particular, we would like to add a branch predictor, register renaming and a memory subsystem hierarchy to the model. The identified set of features are listed here as issues in the repository: https://github.com/riscv-software-src/riscv-perf-model/issues We invite mentees who are passionate about computer architecture and performance modeling to join us in this effort. This is an excellent opportunity to develop a key piece of software that will have high visibility and utility across the entire RISCV community, both in industry and academia. This also presents an opportunity to work with veteran engineers from industry involved in this project.