Micro Electronics Research Lab - UITU

Mentors: Student: Mahnoor_Ismail

AEGIS automates hardware verification by using AI to generate optimized test cases. Parses Specifications: Extracts key features (interfaces, protocols) from documents using NLP. Generates Tests: Creates corner-case and compliance tests via ML models. Optimizes Prioritization: Uses RL to maximize coverage efficiency. Outputs UVM Code: Auto-generates UVM testbenches for simulation.

Mentors: Student: Atharva Nerkar

This project focuses on integrating a Ternary Content Addressable Memory (TCAM) module into the Chipyard SoC framework to enable high-speed parallel matching operations crucial for domains like networking and pattern recognition—functionality not natively supported in Chipyard. The integration employs a dual approach: first, incorporating the Verilog-based TCAM IP (generated via OPENTCAM) as a memory-mapped I/O (MMIO) peripheral by wrapping it in a Chisel BlackBox, connecting it to the subsystem using TileLink, and exposing TCAM operations like write and search through memory-mapped registers accessible from software; and second, integrating the TCAM as a RoCC accelerator by reusing the BlackBox within a custom LazyRoCC module, mapping Rocket’s RoCC interface to TCAM operations via funct fields of custom instructions, and enabling instantiation through a dedicated WithTCAMRoCC configuration in the Rocket tile.

Mentors: Student: Muhammad Hussain_017

This project aims to develop and benchmark high-performance applications that leverage the modular SoC-Now platform, which integrates RISC-V cores, a vector coprocessor (Vaquita), and a post-quantum cryptography accelerator (Baby Kyber). The project will focus on building real-world applications such as image processing, machine learning inference, and secure communication, utilizing Vaquita for vectorized computing and Baby Kyber for post-quantum encryption. These applications will be designed, implemented, and tested on the SoC-Now platform, demonstrating the practical benefits of these hardware accelerators. The goal is to provide the open-source community with reusable application code and detailed performance benchmarks, showcasing the capabilities of SoC-Now in secure computing and efficient AI acceleration. The project will include the development of hybrid applications combining cryptography and vector processing, along with complete documentation and tutorials to make it easy for future developers to leverage the platform for their own projects. Deliverables will include working applications, performance benchmarks, and reusable code packaged for community use, with future work aiming to expand the scope with additional cryptographic primitives, AI models, and improved software stack integration.

Mentors: Student: Abdul_Rehman

Verification in hardware design is a time-consuming and complex task as well as requires manual effort to update UVM testbench components (scoreboard, driver, sequencer) with constant changing DUT. This project proposes to solve this by using AI and NLP to extract key information from the provided DUT specs and updating the UVM components accordingly. This will reduce the manual effort of updating the components and optimize the process of verification. Project Deliverables are : An NLP-based parser for extracting DUT parameters Automated UVM component generation and adaptation Reinforcement learning for better verification environment

Mentors: Student: Nitin Grandhi

With the increasing adoption of RISC-V as an open-source Instruction Set Architecture (ISA), there is a growing need for effective and reusable verification methodologies. While Traditional verification methodologies struggle with variability of RISC-V cores leading to extensive testbench modifications, our project resolves this by leveraging the RISC-V Formal Interface (RVFI) and PyUVM making UVM-based verification more accessible to a broader audience.