lowRISC

Mentors: Student: Yuichi Sugiyama

<p>Pointer Authentication is a software security primitive that makes it much harder for an attacker to aggravate attacks targeting arbitrary code execution through malicious manipulation of code and data pointers. This project aims at doing a proof-of-concept integration of pointer authentication into Ibex.</p> <p>The focus lies on integrating pointer authentication into Ibex's processor pipeline. To this end, new custom instructions need to be added to generate and authenticate pointers. In addition, the Ibex system is 32-bit, so we will need to figure out where to store PAC (Pointer Authentication Codes) and how to load them.</p>

Mentors: Student: Flavien Solt

<h3>Project goal</h3> <p>The goal of this project is to devise and implement a simulation-ready memory controller dedicated to benchmarking processor cores implemented on field programmable logic, that will produce delays much closer to a system where the memory interface is running at a much slower clock speed. This can take two forms.</p> <ul> <li>A simulation model for a memory controller that is tunable.</li> <li>A synthesizable module to be placed between the soft core implementation and an existing non-tunable DRAM controller.</li> </ul> <h3>Novelty and benefits to the community</h3> <p>So far, papers have been reluctant to provide accurate processor core performance figures extrapolated from FPGA implementation because DRAM controllers have an unrealistically high clock speed clock speed relatively to a soft core, compared to an ASIC core implementation. Providing the community with open source tunable memory controller models dedicated to the benchmarking of soft cores will greatly help producing more accurate and interpretable core and accelerator performance figures without requiring an ASIC tape-out in the first place, which is often not even an option.</p>

Mentors: Student: Yeonju Ro

<p>Memory access is one of the most important operation done in modern processors thus it plays an important role in implementation of trusted execution environment. Recent secure processors and trusted environment encrypt memory contents to protect those important memory operations. However, sometimes just encrypting data is not enough since there are intelligent attackers who can see where the memory access goes to and infer where the real important data lies in. Those important data includes the private data, key, or OS fingerprint and else. These kind of attacks lead to concept of “memory obliviousness” to secure memory address itself. ORAM refers to Oblivious memory which can leverage obliviousness using specialized data structures and obfuscate memory access so even an attacker see or probe the memory access itself, he never learns about where important data lies on or even where the memory requests are headed to. Initially proposed by Goldreich and Ostrovsky, ORAM obfuscates memory access using random permutation, shuffling and encryption of contents. In this proposal, I’ll implement ORAM interface to support obliviousness on RISC-V’s trusted execution environment.</p>

Mentors: Student: nchronas

<p>The upgraded role of cubesats, fueled by technological advances in the aerospace industry, that lower launch costs, has opened access to space for a wider audience. Space is a harsh environment for microelectronics. Radiation induced Single Event Upsets can trigger bit flips in memory that could have catastrophic consequences rendering a cubesat useless. Current state of fault tolerance is to either use Rad-Hard electronics that their cost makes it suitable only for high profile missions or the use of Commercial off-the-shelf electronics that offer little protection.</p> <p>My proposal is to modify the lowRISC SoC, employing the Core Lock Step fault tolerant technique in minion cores by integrating a CLS assist unit, in order to be suitable for use in a cubesat mission.</p>

Mentors: Student: Mostafa Saleh

<p>I will implement ARM CMSIS library on PULPino using proposed priority, then i will port the implementation to its DSP core and compare results.</p>