LFX Mentorship Active 2026
Implementation of Tightly-Coupled Data-Flow Integrity in RISC-V
RISC-V1 Program Years
Implementation of Tightly-Coupled Data-Flow Integrity in RISC-V
Open Source
About the Organization
<p>Data-Flow Integrity (DFI) offers robust protection against memory corruption by ensuring that runtime data flow matches a program's static data-flow graph. However, software DFI suffers from prohibitive overhead. Recent hardware solutions attempt to mitigate this by using decoupled coprocessors (e.g., RvDfi) or alternative architectures, but a tightly coupled approach that extends the ISA directly within the pipeline offers a compelling opportunity to optimize performance and area.</p><p><br></p><p>In a collaboration between the SUSHI research team (Inria Rennes) and the Barcelona Supercomputing Center (BSC), this mentorship implements tightly-coupled DFI in the open-source RISC-V Sargantana core. To ensure a realistic scope, the project is structured in two phases. Phase 1 focuses on hardware: the mentee will collaborate with a student at SUSHI who developed preliminary RTL modifications for the CVA-6 core. This accelerates porting and optimization of these ISA extensions for Sargantana.</p><p><br></p><p>Once the hardware is stable, Phase 2 explores the software stack. To keep the project tractable, the goal is an initial, proof-of-concept toolchain integration. The mentee will leverage adaptations started by SUSHI, using the RVDFI toolchain as a baseline. SUSHI's LLVM experts will provide guidance to help the mentee establish a foundational compiler backend. This phased approach guarantees a solid hardware deliverable while ensuring a full-stack proof-of-concept remains an achievable stretch goal.</p>
Primary Technologies & Languages
hardware design (systemverilog, rtl)computer architecturedevelopment tools (linux, git, makefiles, bash, etc.)compilers (llvm)c/c++static analysishardware design (systemverilogrtl)development tools (linuxgitmakefilesbashetc.)
Technical Topics & Focus Areas
hardware design (systemverilog, rtl)computer architecturedevelopment tools (linux, git, makefiles, bash, etc.)compilers (llvm)c/c++static analysishardware design (systemverilogrtl)development tools (linuxgitmakefilesbashetc.)
Participation Years
Completed Projects Distribution
Annual Completed Projects History
Implementation of Tightly-Coupled Data-Flow Integrity in RISC-VHover over bars to view completed counts
4
3
2
1
0
2026
Projects1
Years Active1
Stackhardware design (systemverilog, rtl)
TierTier 1
Past Projects
Showing 1 of 1 projects. Click any project card for scope, mentors, and proposal studio.
Implementation of Tightly-Coupled Data-Flow Integrity in RISC-V Mentorship Project
Intermediate<p>Data-Flow Integrity (DFI) offers robust protection against memory corruption by ensuring that runtime data flow matches a program's static data-flow graph. However, software DFI suffers from prohibitive overhead. Recent hardware solutions attempt to mitigate this by using decoupled coprocessors (e.g., RvDfi) or alternative architectures, but a tightly coupled approach that extends the ISA directly within the pipeline offers a compelling opportunity to optimize performance and area.</p><p><br></p><p>In a collaboration between the SUSHI research team (Inria Rennes) and the Barcelona Supercomputing Center (BSC), this mentorship implements tightly-coupled DFI in the open-source RISC-V Sargantana core. To ensure a realistic scope, the project is structured in two phases. Phase 1 focuses on hardware: the mentee will collaborate with a student at SUSHI who developed preliminary RTL modifications for the CVA-6 core. This accelerates porting and optimization of these ISA extensions for Sargantana.</p><p><br></p><p>Once the hardware is stable, Phase 2 explores the software stack. To keep the project tractable, the goal is an initial, proof-of-concept toolchain integration. The mentee will leverage adaptations started by SUSHI, using the RVDFI toolchain as a baseline. SUSHI's LLVM experts will provide guidance to help the mentee establish a foundational compiler backend. This phased approach guarantees a solid hardware deliverable while ensuring a full-stack proof-of-concept remains an achievable stretch goal.</p>