LFX Mentorship
Hardware Abstraction Layer Transitional Library for Software to Hardware Posits For RISC-V - Part II
RISC-V1 Program Years
Hardware Abstraction Layer Transitional Library for Software to Hardware Posits For RISC-V - Part II
Open Source
About the Organization
This project aims to ease the transition and implementation of Posits, an alternative numerical representation, for RISC-V systems. By creating a robust hardware abstraction layer (HAL), developers need not know if the target RISC-V platform has a hardware Posits implementation or requires a software implementation. This new POSIX-compliant C++ library (with ports planned eventually) will help make available the option to transition between IEEE Float / Doubles to Posits and should make the machine-specific selection and configuration seamless. The lack of such a HAL is a roadblock in Posit adoption and Posits represent a serious opportunity for free and open source silicon (FOSSi) systems. We will also update the existing posit implementations to the current standard and add consistent unit testing. Initial focus will be directed toward HPC support, where numerical computation efficiency may be best observed. Additionally, we will be conducting benchmarking studies to evaluate the performance of the HAL, identifying bottlenecks, and iterating on the design based on empirical data. The testing framework will also be part of the mentee's deliverables.
Primary Technologies & Languages
c++linuxsuccessfully completed a software engineering coursepositsversion controlhalslibrary designqemu would be helpful but is not required to start
Technical Topics & Focus Areas
c++linuxsuccessfully completed a software engineering coursepositsversion controlhalslibrary designqemu would be helpful but is not required to start
Participation Years
Completed Projects Distribution
Annual Completed Projects History
Hardware Abstraction Layer Transitional Library for Software to Hardware Posits For RISC-V - Part IIHover over bars to view completed counts
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2025
Projects1
Years Active1
Stackc++
TierTier 1
Past Projects
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Hardware Abstraction Layer Transitional Library for Software to Hardware Posits For RISC-V - Part II Mentorship Project
IntermediateThis project aims to ease the transition and implementation of Posits, an alternative numerical representation, for RISC-V systems. By creating a robust hardware abstraction layer (HAL), developers need not know if the target RISC-V platform has a hardware Posits implementation or requires a software implementation. This new POSIX-compliant C++ library (with ports planned eventually) will help make available the option to transition between IEEE Float / Doubles to Posits and should make the machine-specific selection and configuration seamless. The lack of such a HAL is a roadblock in Posit adoption and Posits represent a serious opportunity for free and open source silicon (FOSSi) systems. We will also update the existing posit implementations to the current standard and add consistent unit testing. Initial focus will be directed toward HPC support, where numerical computation efficiency may be best observed. Additionally, we will be conducting benchmarking studies to evaluate the performance of the HAL, identifying bottlenecks, and iterating on the design based on empirical data. The testing framework will also be part of the mentee's deliverables.