LFX Mentorship
Enhancement to Olympia
RISC-V1 Program Years
Enhancement to Olympia
Open Source
About the Organization
RISC-V Performance Modeling SIG is driving the development of Performance Modeling and Simulation Tools for use across RISCV membership to foster collaboration across the community. To that end, the SIG has developed a trace-driven performance model of an example RISC-V superscalar processor using C++ based on the Sparta simulation framework. The performance model, named Olympia, has been adopted by multiple organizations in both industry and academia. We have identified set of features for further development of Olympia: * Add support for execution-driven modeling - https://github.com/riscv-software-src/riscv-perf-model/issues/14 * Model state of art branch predictors along with decoupled frontend using branch-prediction API, with an example being the BOOM processor frontend documented at https://docs.boom-core.org/en/latest/sections/branch-prediction/index.html - https://github.com/riscv-software-src/riscv-perf-model/issues/143 - https://github.com/riscv-software-src/riscv-perf-model/issues/1 * Develop an API for Interconnect model and implement an example Interconnect microarchitecture. - https://github.com/riscv-software-src/riscv-perf-model/issues/60 * Use the API for data/instruction prefetcher and implement an example prefetcher microarchitecture - https://github.com/riscv-software-src/riscv-perf-model/issues/142 * Enhance the existing vector extension implementation Etc.
Primary Technologies & Languages
computer architectureperformance modelingcollaborationc++risc-v
Technical Topics & Focus Areas
computer architectureperformance modelingcollaborationc++risc-v
Participation Years
Completed Projects Distribution
Annual Completed Projects History
Enhancement to OlympiaHover over bars to view completed counts
4
3
2
1
0
2024
Projects1
Years Active1
Stackcomputer architecture
TierTier 1
Past Projects
Showing 1 of 1 projects. Click any project card for scope, mentors, and proposal studio.
Performance Model of An Example RISC-V Superscalar Processor
IntermediateRISC-V Performance Modeling SIG is driving the development of Performance Modeling and Simulation Tools for use across RISCV membership to foster collaboration across the community. To that end, the SIG has developed a trace-driven performance model of an example RISC-V superscalar processor using C++ based on the Sparta simulation framework. The performance model, named Olympia, has been adopted by multiple organizations in both industry and academia. We have identified set of features for further development of Olympia: * Add support for execution-driven modeling - https://github.com/riscv-software-src/riscv-perf-model/issues/14 * Model state of art branch predictors along with decoupled frontend using branch-prediction API, with an example being the BOOM processor frontend documented at https://docs.boom-core.org/en/latest/sections/branch-prediction/index.html - https://github.com/riscv-software-src/riscv-perf-model/issues/143 - https://github.com/riscv-software-src/riscv-perf-model/issues/1 * Develop an API for Interconnect model and implement an example Interconnect microarchitecture. - https://github.com/riscv-software-src/riscv-perf-model/issues/60 * Use the API for data/instruction prefetcher and implement an example prefetcher microarchitecture - https://github.com/riscv-software-src/riscv-perf-model/issues/142 * Enhance the existing vector extension implementation Etc.