LFX Mentorship
Compressed instructions for SERV
Linux Foundation1 Program Years
Compressed instructions for SERV
Open Source
About the Organization
The award-winning SERV (https://github.com/olofk/serv) is the world's smallest RISC-V CPU and is suitable for deeply embedded applications where chip area is at a premium. In a real system however, not only the CPU sets the system size and the smaller the CPU, the more important to also minimize the memory size. Adding support for the C ISA extension (compressed instructions) to SERV would enable RISC-V to reach even more use-cases on the deeply embedded side. SERV is an open source bit-serial RISC-V implementation written in Verilog with an emphasis on resource efficiency. The addition of the C ISA extension is expected to consist of changes to the instructions fetcher, an extra optional decoder stage for converting the compressed instructions into their non-compressed equivalents as well as other changes related to the PC not necessarily being word-aligned. On the infrastructure side, the relevant test suites (riscv-formal and riscv-compliance) are expected to pass and it should run the Zephyr operation OS with compressed instructions enabled. The SERV FuseSoC core description file should also be updated to allow users to conditionally select the C ISA extension at compile-time for simulation and FPGA/ASIC targets.
Primary Technologies & Languages
verilogscriptingrisc-vserv
Technical Topics & Focus Areas
verilogscriptingrisc-vserv
Participation Years
Completed Projects Distribution
Annual Completed Projects History
Compressed instructions for SERVHover over bars to view completed counts
4
3
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2022
Projects1
Years Active1
Stackverilog
TierTier 1
Past Projects
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Compressed instructions for SERV Mentorship Project
IntermediateThe award-winning SERV (https://github.com/olofk/serv) is the world's smallest RISC-V CPU and is suitable for deeply embedded applications where chip area is at a premium. In a real system however, not only the CPU sets the system size and the smaller the CPU, the more important to also minimize the memory size. Adding support for the C ISA extension (compressed instructions) to SERV would enable RISC-V to reach even more use-cases on the deeply embedded side. SERV is an open source bit-serial RISC-V implementation written in Verilog with an emphasis on resource efficiency. The addition of the C ISA extension is expected to consist of changes to the instructions fetcher, an extra optional decoder stage for converting the compressed instructions into their non-compressed equivalents as well as other changes related to the PC not necessarily being word-aligned. On the infrastructure side, the relevant test suites (riscv-formal and riscv-compliance) are expected to pass and it should run the Zephyr operation OS with compressed instructions enabled. The SERV FuseSoC core description file should also be updated to allow users to conditionally select the C ISA extension at compile-time for simulation and FPGA/ASIC targets.