CHIPS Alliance

Mentors: Student: Syed Hassan Ul Haq

Our "Support Zvk in T1" project aims to upgrade the T1 processor by adding Zvk, a cryptographic feature from the RISC-V architecture, enhancing its data processing and security capabilities. We'll start with researching how Zvk can fit into the T1's design, then move on to detailed planning and design. The heart of the project is the RTL design and implementation, where we'll turn our plans into a functional model. Testing ensures everything works perfectly, leading to the development of a demo application to showcase the new features. Documentation throughout will provide a blueprint for future advancements. This enhancement will not only improve the T1 processor's performance but also its ability to securely handle data, setting a new standard in the field.

Mentors: Student: Muddassir Ali Siddiqui

I, Muddassir Ali, a final-year Computer Systems Engineering undergraduate student from Pakistan, aim to contribute to the OpenROAD project by implementing a GDS reader/writer. This project aligns with the organization's objectives of enhancing design automation. Throughout the 13-week timeline, I plan to familiarize myself with OpenROAD, study existing classes, learn the GDS-II format, and implement GDSIn and GDSOut classes within OpenROAD. I express a commitment beyond GSoC, ensuring consistent involvement despite final-year project milestones and exams. With strong programming skills in Verilog, C++, and Python, along with a dedication to contribute meaningfully, I aim to deliver seamless integration of GDS functionalities into OpenROAD, thereby strengthening its position in the industry.

Mentors: Student: Fangzhong (Barry) Lyu

This Project adds GDS input and output features to OpenRoad. It would replace the current GDS manipulation scheme, which is through Klayout, and further OpenRoad's capability to provide a tightly integrated RTL-to-GDSII flow.

Mentors: Student: Chetanya Goyal

The proposal seeks to build upon an existing relational framework that facilitates the generation of DRC-compliant analog layouts through conversational English prompts. It addresses challenges in analog layout creation, such as the necessity of coding expertise with Glayout API or the time-intensive nature of GUI-based approaches, as well as the need for automatic layout generation from high-level circuit descriptions. The strategy involves rectifying existing framework bugs and enhancing layout validation through Magic DRC and LVS checks. Subsequently, the framework will be reinforced by simplifying routing and enabling streamlined creation of diverse circuits in a single step. Finally, the framework will be expanded by integrating in a Large Language Model (LLM) to translate very general conversational prompts into simpler commands usable by the relational model.

Mentors: Student: Abhishek_Anand

F4PGA is an open-source FPGA toolchain designed as a free alternative to proprietary computer-aided design tools like Xilinx’s Vivado. Currently, mapping designs to DSP blocks and generating DSP block bitstreams are not implemented for the Xilinx 7-series FPGA devices within the toolchain. This project aims to integrate DSP48E hard block in F4PGA. This will enable designs using DSPs to be synthesized, placed, and routed correctly. We need to diagnose and implement required changes throughout the F4PGA toolchain, allowing for DSP design bitstreams to be successfully generated with open-source tools. Deliverables: 1. Support for DSP48E within the F4PGA architecture definitions. 2. Testing flow for designs using Xilinx 7-series DSP hard blocks which include Verilog-to-Bitstream using the F4PGA toolchain, Fasm2bels to re-generate the original netlist from the bitstream output of F4PGA and Proof-test through Vivado to verify the correctness of the netlist.