ArchC

Mentors: Student: Jainesh Doshi

<p>This project is aimed at porting a (cut down version priority) operating system on a simulator to understand the actual performances when implemented on hardware platforms. Functional simulators like ArchC are otherwise ISA dependent that does not give the whole picture needed for the benchmark performance on the actual hardware. This will benefit as direct performance details onto the scheduler and the benchmark programs running on the OS can be extracted from the simulation.</p>

Mentors: Student: Pavani Tripathi

<p>MPSoCBench developed by the ArchC team currently provides four ISA simulators namely ARM, PowerPC, MIPS and SPARC processor models. The ultimate goal of this project is to make the existing MPSoCBench platform more powerful by adding a new processor model based on the open-source RISC-V architecture. By the end of the project one will have a fully functioning RV32IMAFD (also known as RV32G) processor model which will be directly executable on the ArchC simulator. Also, the model will contain files that will allow it to be used with the MPSoCBench platform.</p>